
W25Q64DW
8. BLOCK DIAGRAM
Security Register 3 - 0
Block Segmentation
003000h
002000h
001000h
000000h
0030FFh
0020FFh
0010FFh
0000FFh
xxFF00h
?
xxF000h
xxEF00h
?
Sector 15 (4KB)
Sector 14 (4KB)
xxFFFFh
?
xxF0FFh
xxEFFFh
?
7FFF00h
? Block 127 (64KB)
7F0000h
7FFFFFh
?
7F00FFh
xxE000h
xxDF00h
xxE0FFh
xxDFFFh
?
xxD000h
xx2F00h
?
xx2000h
Sector 13 (4KB)
?
?
?
Sector 2 (4KB)
?
xxD0FFh
xx2FFFh
?
xx20FFh
?
?
?
xx1F00h
?
xx1000h
xx0F00h
?
xx0000h
Sector 1 (4KB)
Sector 0 (4KB)
xx1FFFh
?
xx10FFh
xx0FFFh
?
xx00FFh
40FF00h
?
400000h
3FFF00h
?
Block 64 (64KB)
Block 63 (64KB)
40FFFFh
?
4000FFh
3FFFFFh
?
3F0000h
?
3F00FFh
/WP (IO 2 )
Write Control
Logic
20FF00h
?
?
20FFFFh
?
200000h
Block 32 (64KB)
?
2000FFh
Status
Register
1FFF00h
?
1F0000h
Block 31 (64KB)
1FFFFFh
?
1F00FFh
?
High Voltage
Generators
00FF00h
?
?
00FFFFh
/HOLD (IO 3 )
?
000000h
Block 0 (64KB)
?
0000FFh
CLK
/CS
SPI
Command &
Page Address
Latch / Counter
Beginning
Page Address
Ending
Page Address
DI (IO 0 )
DO (IO 1 )
Control Logic
Data
Byte Address
Column Decode
And 256-Byte Page Buffer
Latch / Counter
Figure 2. W25Q64DW Serial Flash Memory Block Diagram
Publication Release Date: September 18, 2012
-9-
Revision D